With the development of arc welding inverter to high frequency and high power density

the influences of parasitic parameters become more critical with the high voltage and current slew rate. Modeling of power semiconductor modules in the absence of data of chip technology and electrical parameters is common problem for system designer. To solve this problem

a high efficiency and practical method for extracting parasitic parameters inside packaging is presented. Splitting interconnect conductors based on the principle of partial element equivalent circuit

PEEC. The numerical calculation of quasi-static electromagnetic field is carried out for one unit with the same geometric structure using ANSYS Q3 D. Parasitic inductance and resistance parameter matrix is extracted. By merging and reducing equivalent circuit

the complete module model including parasitic inductance

resistance and capacitance is built. The parameters of the model are provided for an IGBT module of SKM200 GB125 D as an example. Using double pulse test method

the switching behavior is simulated and measured. The accuracy of the model and validity of the modeling method is verified by the comparison between the simulated and experimental results.